1. Field of the Invention
The invention relates to a non-volatile semiconductor memory device which stores data by trapping charge in a multilayer film composed of a plurality of insulating films, a fabricating method of the same, and a semiconductor memory system including the non-volatile semiconductor memory device and a power supply unit.
2. Description of the Related Art
A non-volatile semiconductor memory stores data by storing charge in a charge storage film. EEPROMs (Electronically Erasable and Programmable Read Only Memories) are roughly classified into two kinds of structures whose charge storage films are different in kinds from each other. One is a FG (Floating Gate) type in which a conductor called a floating gate serving as a charge storage film which is surrounded by an oxide film or the like to be electrically insulated is provided on a gate insulation film, and charge is stored in the floating gate. The other is a MNOS (Metal-Nitride-Oxide-Silicon) type or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that has a charge storage film composed of a plurality of stacked insulating films and stores data by controlling an amount of charge stored in a charge trap in the charge storage film.
To store charge in a charge storage film, there are a FN (Fowler-Nordheim tunneling) writing method utilizing a tunnel effect of the charge in the insulating films and a method called CHE (Channel Hot Electron) injection that energetically excites the charge up to a degree so that the charge can cross over an insulating barrier of the insulating film on the bottom layer. There have been many proposals for this method of injecting the excited charge (see, for example, JP2004-214365A).
A prior art disclosed in JP2004-214365A will now be described. FIG. 23 is a schematic cross-sectional view to illustrate the structure of a MONOS-type non-volatile semiconductor memory device which is one of the EEPROMs, and certain changes are made in the drawing for easier explanation within a range not departing from the spirit of the prior art disclosed in JP2004-214365A.
In FIG. 23, each numeral denotes that 10 is a MONOS-type non-volatile semiconductor memory device, 11 is a p-type semiconductor substrate, 12 is an n-type source region, 13 is an n-type drain region, 24 is a multilayer film composed of three layers of insulating films, and 15 is a gate electrode.
The multilayer film 24 is composed of a tunnel oxide film 241 that is the closest to the semiconductor substrate 11, a memory nitride film 242 being a silicon nitride film on an intermediate layer, and a top oxide film 243 provided on the uppermost layer.
In the semiconductor substrate 11 of the non-volatile semiconductor memory device 10, a p-type heavily doped region 16 higher in impurity concentration than the semiconductor substrate 11 is further provided in an end portion in contact with the drain region 13, in a channel region 17 between the source region 12 and the drain region 13. The multilayer film 24 is provided on top of the channel region 17.
At the time of data write, with a potential of the source region 12 being a reference, a writing drain voltage is applied to the drain region 13 and a writing gate voltage is applied to the gate electrode 15. Consequently, electrons being minority carriers for the p-type semiconductor substrate 11 are supplied from the source region 12 whose potential is used as the reference. The minority carriers are accelerated by an electric field in a channel direction in the channel region 17. In the channel region, the minority carriers gain high energy in the vicinity of the end of the drain region 13, so that the minority carriers cross over a potential barrier of the tunnel oxide film 241 of the multilayer film 24 and are injected to the multilayer film 24 to be stored in the memory nitride film 242.
At this time, in the channel region 17, concentration of the electric field in the channel direction becomes high in the vicinity of the end of the drain region 13 due to the existence of the heavily doped region 16, so that a larger amount of the charge is efficiently injected to the multilayer film 24 to be stored in the memory nitride film 242.
At the time of data read, with a potential of one of the source region 12 and the drain region 13 being a reference, a reading voltage is applied to the other and a reading gate voltage is applied to the gate electrode 15. Since a threshold value of the gate voltage at which a current starts to flow between the source region 12 and the drain region 13 changes according to an amount of the charge stored in the multilayer film 24, it is possible to determine whether or not there exists stored data (to read the stored data), based on the magnitude or the existence or not of the source-drain current when the reading voltage is applied to the MONOS-type non-volatile semiconductor memory device in the above-described manner.
Similarly to the time of writing, due to the existence of the heavily doped region 16, the concentration of the electric field in the channel direction also becomes higher in part at this time, but no energy high enough for the electrons to cross over the potential barrier of the tunnel oxide film 241 is given, and thus erroneous write is prevented.
At the time of data erase, with a potential of the semiconductor substrate 11 being a reference, a positive voltage is applied to the drain region 13 and a negative voltage is applied to the gate electrode 15.
Consequently, charge (holes) opposite in polarity to the written charge (electrons) is supplied into the multilayer film 24 from the drain region 13 and the charges different in polarity are coupled in the memory nitride film 242 to be neutralized, whereby data is erased.
The prior art disclosed in this patent document is capable of realizing a decrease in writing voltage since a larger amount of charge is efficiently injected to the multilayer film 24 at the time of data write owing to the existence of the heavily doped region 16. Another characteristic thereof is that at the time of reading, no unnecessary charge is injected to the multilayer film 24 and therefore, no erroneous write occurs.
As described above, the non-volatile semiconductor memory device includes the heavily doped region 16, thereby improving efficiency of the injection of the charge to the multilayer film 24 on top of the heavily doped region 16, but to further improve the efficiency at the time of data write, the writing gate voltage applied to the gate electrode 15 has to be made higher. As a result, an amount of the charge injected to the multilayer film 24 on top of the heavily doped region 16 increases.
However, since the thickness of the multilayer film 24 is uniform on the whole channel region 17, a high electric field is applied to the whole channel region. Consequently, there is a certain probability that the charge (electrons) is injected to the multilayer film 24 from a region before reaching the heavily doped region 16, even though the charge should be injected to the multilayer film 24 after gaining higher energy near the heavily doped region 16 close to the end of the drain region 13 in the channel region 17.
The increase in the writing gate voltage applied to the gate electrode 15 also increases its difference from the writing drain voltage applied to the drain region 13, so that the charge generated in the vicinity of the source region 12 is not accelerated sufficiently due to an electric field in a direction orthogonal to the electric field in the channel direction of the channel region 17. Consequently, even if the charge reaches the vicinity of the drain region 13, it cannot gain energy high enough to cross over the potential barrier of the multilayer film 24, which may possibly prevent normal write itself.
If normal injection of the charge to a predetermined portion of the multilayer film 24 thus decreases and the charge is injected to an unintended portion, a threshold value of the non-volatile semiconductor memory device becomes different from that when normal write is performed.
Since such a situation is a kind of erroneous write and data is not normally written, a write state is not stable and the threshold value after the write cannot be controlled.
A write state or an erase state of a non-volatile semiconductor memory device is known from a change in its threshold value. That is, based on a range in which the threshold value falls, the meaning of written data is determined. Therefore, if the threshold value becomes an unintended value, the meaning of the data becomes erroneous at an instant the data is written, or a margin for fluctuation of the threshold value with the elapse of time, that is, a data retention characteristic, deteriorates. In either case, reliability as a storage device deteriorates.
Further, as for semiconductor devices in recent years, a demand for a lower driving voltage is arising in accordance with the miniaturization and increase in integration density of semiconductor elements. Non-volatile semiconductor memory devices are also under the same circumstances, but as for the memory devices, there is also a demand for a decrease in writing voltage and erasing voltage. However, increasing the writing gate voltage for higher efficiency of data write as described above is contrary to the demand.
Therefore, such a non-volatile semiconductor memory device had problems that, for executing more efficient write, it is necessary to increase a writing gate voltage applied to a gate electrode, and as a result, the non-volatile semiconductor memory device becomes unstable and cannot respond to the demand for a lower voltage that has arisen in accordance with the miniaturization of the recent semiconductor devices.
Further, a multi-level memory has been drawing attention as a non-volatile semiconductor memory. The multi-level memory, which stores a plurality of data in one memory element, can store a larger data volume in each memory element, and therefore has been drawing attention as an art that can dramatically increase a data storage amount even with the same integration degree of memory chips.
However, the above-described non-volatile semiconductor memory device cannot be used as a multi-level memory.